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| a FEATURES 10 MHz-300 MHz Input Frequency Baseband (I/Q) Digital Output 10 kHz-150 kHz Output Signal Bandwidth 12 dB SSB NF > -1 dBm IIP3 (High IIP3 Mode) 25 dB Continuous AGC Range + 16 dB Gain Step Support for LO and Sampling Clock Synthesis Programmable Decimation Rate, Output Format, AAF Cutoff, AGC and Synthesizer Settings 360 Input Impedance 2.7 V-3.6 V Supply Voltage Low Current: 42 mA Typ (High IIP3 Mode), 30 mA Typ (Low IIP3, Fixed Gain Mode) 48-Lead LQFP Package (1.4 mm Thick) APPLICATIONS Portable and Mobile Radio Products Digital UHF/VHF FDMA Products TETRA IF Digitizing Subsystem AD9870 PRODUCT DESCRIPTION The AD9870 is a general-purpose IF subsystem that digitizes a low-level 10 MHz-300 MHz IF input with a bandwidth of up to 150 kHz. The signal chain of the AD9870 consists of a low-noise amplifier, a mixer, a variable gain amplifier with integral antialias filter, a bandpass sigma-delta analog-to-digital converter, and a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit provides the AD9870 with 25 dB of continuous gain adjustment. The high dynamic range of the bandpass sigma-delta converter allows the AD9870 to cope with blocking signals that are as much as 70 dB stronger than the desired signal. Auxiliary blocks include clock and LO synthesizers as well as a serial peripheral interface (SPI) port. The SPI port programs numerous parameters of the AD9870, including the synthesizer divide ratios, the AGC attack and decay times, the AGC target signal level, the decimation factor, the output data format, the 16 dB attenuator, and the bias currents of several blocks. Reducing bias currents allows the user to reduce power consumption at the expense of reduced performance. FUNCTIONAL BLOCK DIAGRAM MXOP MXON GCP GCN IF2P IF2N AD9870 -16dB IFIN FREF LO SYNTH SAMP CLOCK SYNTHESIZER LNA VGA/ AAF DAC AGC - ADC fCLK = 18MHz DECIMATION FILTER FORMATTING/SSI DOUTA DOUTB FS CLKOUT CONTROL LOGIC VOLTAGE REFERENCE SPI IOUTC CLKN CLKP VCM LON LOP PC PD PE LO VCO AND LOOP FILTER CLK VCO AND LOOP FILTER REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001 SYNCB VREFN VREFP IOUTL AD9870-SPECIFICATIONS VDDP = 5.0 V, CLK = 18 MSPS, F = 73.35 MHz, F Parameter OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) Digital Supply Voltage (VDDD, VDDC, VDDL) Interface Supply Voltage (VDDH) Charge Pump Supply Voltage (VDDP, VDDQ) Total Current SSB Noise Figure @ Max VGA Gain Input Third-Order Intercept (IIP3) Input Impedance Gain Variation Over Temperature PREAMP + MIXER Maximum Input and LO Frequencies LO SYNTHESIZER LO Input Frequency LO Input Amplitude FREF (Reference) Frequency FREF Input Amplitude Minimum Charge Pump Output Current Maximum Charge Pump Output Current Charge Pump Output Compliance Voltage2 Synthesizer Resolution CLOCK SYNTHESIZER CLK Input Frequency CLK Input Amplitude Minimum Charge Pump Output Current Maximum Charge Pump Output Current Charge Pump Output Compliance Voltage2 Synthesizer Resolution SIGMA-DELTA ADC Resolution Clock Frequency (fCLK) Center Frequency Dynamic Range Passband Gain Variation DECIMATOR Decimation Factor Passband Width Passband Gain Variation Alias Attenuation GAIN CONTROL Programmable Gain Step AGC Gain Range (Continuous) AGC Attack Time SPI PC Clock Frequency PD Hold Time SSI CLKOUT Frequency Output Rise/Fall Time 7.75 0.3 0.1 0.3 Programmable in 0.625 mA Steps Programmable in 0.625 mA Steps 0.25 6.25 13 0.3 Conditions1 Min 2.7 2.7 1.8 2.7 High IIP3 Setting High IIP3 Setting Low IIP3 Setting High IIP3 Setting Low IIP3 Setting (VDDI = VDDF = VDDA = 3.3 V, VDDC = VDDL = 3.3 V, VDDD = VDDH = 3.3 V, VDDQ = IF LO = 71.1 MHz, unless otherwise noted.) Typ Max Unit 3.0 3.0 3.6 3.6 3.6 V V V V mA dB dB dBm dBm dB MHz -5 3.0 42 12 12 -1 -10 360 0.6 300 5.5 50.6 300 1.0 25 3 0.625 5.000 VDDP - 0.25 MHz V p-p MHz V p-p mA mA V kHz MHz V p-p mA mA V kHz Bits MHz MHz dB dB 18 0.625 5.000 Clock VCO Off Programmable in 0.625 mA Steps Programmable in 0.625 mA Steps 0.25 2.2 16 13 BW = 10 kHz fCLK/8 88 VDDQ - 0.25 18 0.5 Programmable in Steps of 60 60 50 85 16 25 960 1 % dB dB dB dB s MHz ns MHz ns ns ns ns C C Programmable 18 40 60 7000 10 10 1 CMOS Output Mode, Drive Strength = 0 CMOS Output Mode, Drive Strength = 1 CMOS Output Mode, Drive Strength = 2 CMOS Output Mode, Drive Strength = 3 -40 -40 18 120 45 16 10 +95 +85 OPERATING TEMPERATURE RANGE Basic Functions Meets All Specifications NOTES 1 Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, 25 pF load on SSI output pins: VDDx = 3.0 V. 2 Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2). Specifications subject to change without notice. -2- REV. 0 AD9870 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Unit VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDP, VDDQ GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDQ, GNDP, GNDS MXOP, MXON, LOP, LON, IFIN, CXIF, CXVL, CXVM PC, PD, PE, CLKOUT, DOUTA, DOUTB, FS, SYNCB IF2N, IF2P, GCP, GCN VREFP, VREFN, VCM IOUTC IOUTL CLKP, CLKN FREF Junction Temperature Storage Temperature Lead Temperature (10 sec) GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDS VDDR, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI GNDP, GNDQ GNDF, GNDA, GNDC, GNDD, GNDH GNDL, GNDI, GNDQ, GNDP, GNDS GNDI GNDH GNDF GNDA GNDQ GNDP GNDC GNDL -0.3 -4.0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -65 +4.0 +4.0 +6.0 +0.3 VDDI + 0.3 VDDH + 0.3 VDDF + 0.3 VDDA + 0.3 VDDQ + 0.3 VDDP + 0.3 VDDC + 0.3 VDDL + 0.3 150 +150 300 V V V V V V V V V V V V C C C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP JA = 91C/W JC = 28C/W ORDERING GUIDE Model AD9870 AD9870EB Temperature Range -40C to +85C Package Description 48-Lead Thin Plastic Quad Flatpack (LQFP) Evaluation Board Package Option ST-48 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9870 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -3- AD9870 PIN CONFIGURATION IOUTL GNDP LOP LON CXVM VDDL VDDP 48 47 46 45 44 43 42 41 40 39 38 37 MXOP 1 MXON 2 GNDF 3 IF2N 4 IF2P 5 VDDF 6 GCP 7 GCN 8 VDDA 9 GNDA 10 VREFP 11 VREFN 12 IFIN CXIF GNDI CXVL VDDI PIN 1 IDENTIFIER 36 35 34 33 GNDL FREF GNDS SYNCB GNDH FS DOUTB DOUTA CLKOUT VDDH VDDD PE AD9870 TOP VIEW (Not to Scale) 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 VDDQ IOUTC GNDQ VDDC PIN FUNCTION DESCRIPTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic Description MXOP MXON GNDF IF2N IF2P VDDF GCP GCN VDDA GNDA VREFP VREFN VCM VDDQ IOUTC GNDQ VDDC GNDC CLKP CLKN GNDS GNDD PC PD Mixer Output, Positive Mixer Output, Negative Ground for VGA Second IF Input (to VGA), Negative Second IF Input (to VGA), Positive Positive Power Supply for Antialias Filter/VGA Filter Capacitor for VGA Gain Control, Positive Filter Capacitor for VGA Gain Control, Negative Positive Power Supply for ADC Ground for ADC Voltage Reference, Positive Voltage Reference, Negative Common-Mode Voltage (Requires 20 k to GNDA) Pos. Power Supply for Clock Synth. Charge Pump Clock Synthesizer Charge Pump Output Current Ground for Clock Synthesizer Charge Pump Positive Power Supply for Clock Synthesizer Ground for Clock Synthesizer Sampling Clock Input/Clock VCO Tank, Positive Sampling Clock Input/Clock VCO Tank, Negative Substrate Ground Ground for Digital Functions Clock Input for SPI Port Data I/O for SPI Port Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Mnemonic PE VDDD VDDH CLKOUT DOUTA DOUTB FS GNDH SYNCB GNDS FREF GNDL GNDP IOUTL VDDP VDDL CXVM LON LOP CXVL GNDI CXIF IFIN VDDI Description Enable Input for SPI Port Positive Power Supply for Internal Digital Functions Positive Power Supply for Digital Interface Clock Output for SSI Port Data Output for SSI Port Data Output for SSI Port, Unused Frame Sync for SSI Port Ground for Digital Interface Resets the SSI and Decimator Counters Substrate Ground Reference Frequency Input for Both Synthesizers Ground for LO Synthesizer Ground for LO Synthesizer Charge Pump LO Synthesizer Charge Pump Output Current Positive Power Supply for LO Synth. Charge Pump Positive Power Supply for LO Synthesizer External Capacitor for Mixer Bias LO Input to Mixer and LO Synthesizer, Negative LO Input to Mixer and LO Synthesizer, Positive External Capacitor for Preamp Power Supply Ground for Mixer and Preamp External Capacitor for Preamp Bias First IF Input (to Preamp) Positive Power Supply for Mixer and Preamp GNDC CLKP CLKN GNDS GNDD VCM -4- PC PD REV. 0 AD9870 SERIAL PERIPHERAL INTERFACE (SPI) The Serial Peripheral Interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed below as well as to read back their contents. Table I provides a list of the registers that may be programmed through the SPI port. Addresses and default values are given in hexadecimal form. Table I. SPI Address Map Address Bit (Hex) Breakdown Width Default Value Name Description POWER CONTROL REGISTERS 0x00 0x01 (7:0) (7:6) (5:4) (3:2) (1:0) (7:0) 8 2 2 2 2 8 0xFF 0 0 0 1 0x00 STBY LNAB MIXB CKOB ADCB TEST Standby Control Bits (REF, LO, CKO, CK, GC, LNAMX, VGA, ADC). LNA Bias Current (0 = 0.5 mA, 1 = 1 mA, 2 = 2 mA, 3 = 3 mA). Mixer Bias Current (0 = 1 mA, 1 = 2 mA, 2 = 3 mA, 3 = 4 mA). CK Oscillator Bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.53 mA, 3 = 0.85 mA). ADC Amplifier Bias (0 = 2.4 mA, 1 = 3.2 mA, 2 = 4.0 mA, 3 = 4.8 mA). Factory Test Mode. 0x02 AGC 0x03 0x04 0x05 0x06 (7) (6:0) (7:0) (7:4) (3:0) (7:4) (3:0) (2:0) 1 7 8 4 4 4 4 3 0 0x3F 0xFF 0 0 0 0 0 ATTEN Apply 16 dB attenuation in the front end. AGCG(14:8) AGC Gain Setting (7 MSBs of a 15-bit two's-complement word). AGCG(7:0) AGCA AGCD AGCO AGCD AGCR AGC Gain Setting (8 LSBs of a 15-bit two's-complement word). Default corresponds to maximum gain. AGC Attack Time Setting. Default yields 50 Hz raw loop bandwidth. AGC Decay Time Setting. Default is decay time = attack time. AGC Overload Update Setting. Default is slowest update. Fast AGC (Minimizes resistance seen between GCN and GCP). AGC Enable/Reference Level (disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB below clip). DECIMATION FACTOR 0x07 (3:0) 4 4 M Decimation Factor = 60 x (M + 1). Default is decimate-by-300. LO SYNTHESIZER 0x08 0x09 0x0A (5:0) (7:0) (7:5) (4:0) (7:0) (6) (5) (4:2) (1:0) (3:0) (7:0) 6 8 3 5 8 1 1 3 2 4 8 0x00 0x38 0x5 0x00 0x1D 0 0 0 0 0x0 0x04 LOR(13:8) LOR(7:0) LOA LOB(12:8) LOB(7:0) LOF LOINV LOI LOTM LOFA(13:8) LOFA(7:0) Reference Frequency Divisor (6 MSBs of a 14-Bit Word). Reference Frequency Divisor (8 LSBs of a 14-Bit Word). Default (56) Yields 300 kHz from fREF = 16.8 MHz. "A" Counter (Prescaler Control Counter). "B" Counter MSBs (5 MSBs of a 13-Bit Word). Default LOA and LOB Values Yield 300 kHz from 73.35 MHz-2.25 MHz. "B" Counter LSBs (8 LSBs of a 13-Bit Word). Enable Fast Acquire. Invert Charge Pump (0 = Pump_Up IOUTL Sources Current). Charge Pump Current in Normal Operation. IPUMP = (LOI + 1) x 0.625 mA. Manual Control of LO Charge Pump (3 = Off, 2 = Down, 1 = Up, 0 = Normal). LO Fast Acquire Time Unit (4 MSBs of a 14-Bit Word). LO Fast Acquire Time Unit (8 LSBs of a 14-Bit Word). 0x0B 0x0C 0x0D 0x0E CLOCK SYNTHESIZER 0x10 0x11 (5:0) (7:0) 6 8 00 0x38 CKR(13:8) CKR(7:0) Reference Frequency Divisor (6 MSBs of a 14-Bit Word). Reference Frequency Divisor (8 LSBs of a 14-Bit Word). Default Yields 300 kHz from fREF =16.8 MHz. Min = 3, Max = 16383. Synthesized Frequency Divisor (5 MSBs of a 13-Bit Word). 0x12 (4:0) 5 0x00 CKN(12:8) REV. 0 -5- AD9870 Address Bit (Hex) Breakdown Width Default Value Name Description CLOCK SYNTHESIZER (Continued) 0x13 (7:0) 8 0x3C CKN(7:0) Synthesized Frequency Divisor (8 LSBs of a 13-Bit Word). Default Yields 300 kHz from fCLK = 18 MHz. Min = 3, Max = 8191. Enable Fast Acquire. Invert Charge Pump (0 = Pump_Up IOUTC Sources Current). Charge Pump Current in Normal Operation. IPUMP = (CKI + 1) x 0.625 mA. Manual Control of CLK Charge Pump (0 = Off, 1 = Down, 2 = Up, 3 = Normal). 0x14 (6) (5) (4:2) (1:0) (3:0) (7:0) 1 1 3 2 4 8 0 0 0 0 0x0 0x04 CKF CKINV CKI CKTM 0x15 0x16 CKFA(13:8) CK Fast Acquire Time Unit (4 MSBs of a 14-Bit Word). CKFA(7:0) CK Fast Acquire Time Unit (8 LSBs of a 14-Bit Word). SSI CONTROL 0x18 0x19 0x1A (7:0) (1:0) (3:0) 8 2 4 0x12 0x0 1 SSICRA SSICRB SSIORD SSI Control Register A. See Table III. (Default is FS and CLKOUT Three-Stated.) SSI Control Register B. See Table III. Output Rate Divisor. fCLKOUT = fCLK/SSIORD. AAF CAPACITOR SETTING/CALIBRATION 0x1C 0x1D 0x1E (7:0) 5 (4:0) 5 (4:0) 8 1 5 1 15 0x00 0 0x0 0 0x0 AAR ERRN CAPN ERRP CAPP Antialias Response Selector. 0x60 Is Recommended. Error Flag. AAF N-Well Capacitor Setting. Error Flag. AAF Poly-Poly Capacitor Setting. TEST REGISTERS AND SPI PORT READ ENABLE 0x38 0x39 0x3A 0x3B- 0x3F (7:0) 0 (7:4, 2:0) (3) (7:0) 8 1 7 1 1 0x00 0 0x0 0 0x00 TEST TEST TEST SPIREN TEST Factory Test Mode. Factory Test Mode. Factory Test Mode. Enable Read from SPI Port. Factory Test Mode. -6- REV. 0 AD9870 PC PE WRITE OPERATION: PD A5 A0 D7 D6 D0 READ OPERATION: PD A5 A0 D7 D6 D0 Figure 1. SPI Timing Figure 1 illustrates the timing for the SPI port. After the peripheral enable (PE) signal goes low, data (PD) is read on the rising edges of the clock (PC). The first bit is a read/not-write indicator; the next six bits are address bits; the eighth bit is ignored; the last eight bits are data. Address and data are given MSB first. If the read/not-write indicator is a zero, a write operation occurs and the data bits are shifted in. If the read/not-write indicator is a one and if the read-back enable bit (Reg. 3A, Bit 3) has been set, a read operation occurs and data is shifted out the data pin on the falling edges of the clock. PE stays low during the operation and goes high at the end of the transfer. If PE rises before an additional eight clock cycles have passed, the operation is aborted. If PE stays low for an additional eight clock cycles, the destination address is incremented and another eight bits of data are shifted in. Again, should PE rise early, the current byte is ignored. By using this implicit addressing mode, the entire chip can be configured with a single write operation. Registers identified as being subject to frequent updates, namely those associated with power control and AGC operation, have been assigned adjacent addresses to minimize the time required to update them. The autoincrement mode is not supported for read operations. Multibyte registers are "big-endian" (the most significant byte has the lower address) and are updated when a write to the least significant byte occurs. SYNCHRONOUS SERIAL INTERFACE (SSI) Table II. Max Legal SSIORD Values for 16-Bit I/O Data and Decimation by 60 n Bits per Sample (Min No. of Bits per Frame) EAGC = 0 EFS =1 EFS = 0 32 49 EAGC = 1 EFS = 0 EFS = 1 48/40* 69/59* Output Sample Rate Max SSIORD Setting (Decimal) Dec'n (kSPS, for EAGC = 0 EAGC = 1 M Factor fCLK = 18 MHz) EFS = 0 EFS = 1 EFS = 0 EFS = 1 The primary output of the AD9870 is the converted signal, which is available from the SSI port as a serial bit stream. The bit stream consists of a 16-bit I word followed by a 16-bit Q word, where each word is given MSB first and is in two's-complement form. AGC, signal strength, and synchronization information may also be embedded in the data stream. The output bit rate (fCLKOUT) is equal to the modulator clock frequency (fCLK) divided by the contents of the SSIORD register. Users must verify that the output bit rate is sufficient to accommodate the required number of bits per frame (see Table II) and that the chosen output rate does not introduce harmful spurs. Idle (high) bits are used to fill out each frame; the frame lengths listed in Table II assume that with embedded frame sync (EFS = 1), at least 10 idle bits are desired. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 60 120 180 240 300 360 420 480 540 600 660 720 780 840 900 960 300 150 100 75 60 50 42.857 37.5 33.333 30 27.272 25 23.077 21.428 20 18.75 1 3 5 7 9 11 13 14 15 15 15 15 15 15 15 15 1 2 3 4 5 7 8 9 10 11 13 14 15 15 15 15 1 2 3 5 6 7 8 10 11 12 13 14 15 15 15 15 1 1 2 3 4 5 5 6 7 8 9 10 11 11 12 13 *If the AAGC Bit of SSICRA is set. Figure 2 illustrates the output timing of the SSI port for several SSI control register settings. In the default mode of operation, data is shifted out on rising edges of CLKOUT after a pulse is output from the frame sync (FS) pin. As described above, the output data consists of a 16-bit I sample followed by a 16-bit Q sample plus two optional bytes containing AGC and status information. REV. 0 -7- AD9870 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 G15 G14 G0 SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC = 0 CLKOUT FS START BIT HI-Z START BIT START BIT DOUT I15 I8 STOP BIT I7 I0 STOP BIT Q15 IDLE (HIGH) BITS SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0 SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0: AS ABOVE, BUT FS IS LOW CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 Figure 2. SSI Timing for Several SSICR Settings The two optional bytes are output if the EAGC bit of SSICRA is set. The first byte contains the eight most significant bits of the AGC DAC setting while the second byte contains a 2-bit overload field, a 2-bit reset field, a 2-bit large-signal field, a zero bit, and a trailing high bit. The overload, reset, and large-signal fields contain the number of overload, reset, and large-signal events since the last report, respectively, saturating at three should the number of events equal or exceed this amount. The two optional bytes follow the I and Q data as a 16-bit word provided the AAGC bit of SSICRA is not set. If the AAGC bit is set, the two bytes follow the I and Q data in an alternating fashion. In this "alternate AGC data" mode, the LSB of the byte containing the AGC DAC setting is zero; the LSB of the byte containing reset/overload information is always a one. Figure 3 illustrates the fields of the SSI data frames. EAGC = 0, AAGC = X: 32 DATA BITS I (15:0) Q (15:0) EAGC = 1, AAGC = 0: 48 DATA BITS I (15:0) Q (15:0) AGC (7:0) 1 EAGC = 1, AAGC = 1: 40 DATA BITS I (15:0) I (15:0) Q (15:0) Q (15:0) OVERLOAD COUNT RESET COUNT DON'T CARE FGM AGC (7:1) 0 1 SAME Figure 3. SSI Frame Structure -8- REV. 0 AD9870 When the embedded frame sync bit (EFS) is set, FS is either low or in a high Z state (as determined by the SFST bit), and framing information is embedded in the data stream. In this mode, each eight bits of data are surrounded by a start bit (low) and a stop bit (high), and each frame ends with at least 10 high bits. Other control bits can be used to invert the frame sync (SFSI), to delay the frame sync pulse by one clock period (SLFS), to invert the clock (SCKI), or to set the clock (SCKT) to a high Z state. Note that if EFS is set, SLFS is a don't care. The AD9870 also provides the means for controlling the switching characteristics of the digital output signals. With a 25 pF load, the rise and fall times of these signals are no more than 120 ns, 45 ns, 16 ns, or 10 ns if the DS (drive strength) setting is 0, 1, 2, or 3, respectively. Table III. SSI Control Registers GC Table IV. Standby Control Bits Current Reduction (mA)1 1.5 WakeUp Time (ms) 1.0 (CREF = 4.7 F) Note 2 Note 2 Note 2 STBY Bit REF Effect Voltage Reference Off, VREFP, VREFN in High Z State. LO Synthesizer Off, IOUTL in High Z State. Clock Oscillator Off. Clock Synthesizer Off, IOUTC in High Z State. Clock Buffer Off if ADC Is Off. Gain Control DAC Off. GCP, GCN in High Z State. LNA and Mixer Off. I(VDDI) = 0, CXVM, CXVL, CXIF in High Z. VGA/AAF Off. IF2P, IF2N in High Z State. ADC Off; Clock Buffer Off if CK Synth. Off; VCM in High Z State; Clock-to-Digital Filter Suspended; Digital Outputs Static. LO CKO CK 4.8 0.25 1.4 3 10 Name Width Description LNAMX Depends on CGC SSICRA (ADDR = 0x18) AAGC EAGC EFS SFST SFSI SLFS SCKT SCKI 1 1 1 1 1 1 1 1 Alternate AGC Data Bytes Embed AGC Data Embed Frame Sync Three-State Frame Sync Invert Frame Sync Late Frame Sync (1 = Late, 0 = Early) Three-State CLKOUT Invert CLKOUT VGA ADC 6 13.8 0.1 0.1 SSICRB (ADDR = 0x19) DS 2 FS, CLKOUT, and DOUT Drive Strength NOTES 1 When all blocks are in standby, the master reference circuit is also put into standby and thus the current is reduced by a further 0.4 mA. 2 Wake-up time is application-dependent. POWER CONTROL To allow power consumption to be minimized, the AD9870 possesses numerous SPI-programmable power-down and bias control bits. Each major block may be powered down through the appropriate bit of the STBY register. This scheme provides the greatest flexibility for configuring the IC to a specific application as well as for tailoring the IC's power-down and wake-up characteristics. Table IV summarizes the function of each of the STBY bits. Note, when all the blocks are in standby, the master reference circuit is also put into standby and thus the current is reduced by a further 0.4 mA. The AD9870 also allows control over the bias current in several key blocks. The effects on current consumption and system performance are described in the section dealing with the affected block. LO SYNTHESIZER The LO synthesizer shown in Figure 4 is a fully programmable PLL capable of 6.25 kHz resolution at input frequencies up to 300 MHz and reference clocks of up to 25 MHz. It consists of a low-noise digital Phase-Frequency Detector (PFD), a variable output current charge pump (CP), a 14-bit reference divider, programmable A and B counters and a dual-modulus 8/9 prescaler. The A (3-bit) and B (13-bit) counters, in conjunction with the dual 8/9 modulus prescaler, implement an N divider with N = 8 x B + A. In addition, the 14-bit reference counter (R Counter) allows selectable input reference frequencies, fREF, at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator). REV. 0 -9- AD9870 The A, B, and R counters can be programmed via the following registers: LOA, LOB, and LOR. The charge pump output current is programmable via the LOI register from 0.625 mA to 5.0 mA using the following equation: IPUMP = (LOI + 1) x 0.625 mA. An on-chip lock detect function (enabled by the LOF bit) automatically increases the output current for faster settling during channel changes. The synthesizer may also be disabled using the LO standby bit located in the STBY register. FREF R TO EXTERNAL LOOP FILTER Figure 5 shows the equivalent input structures of the synthesizers' LO and REF buffers (excluding the ESD structures). The LO input is fed to the LO synthesizers buffer as well as the AD9870's mixer's LO port. Both inputs are self-biasing and thus tolerate ac-coupled inputs. The LO input can be driven with a single-ended or differential signal. Single-ended dccoupled inputs should ensure sufficient signal swing above and below the common-mode bias of the LO and REF buffers (i.e., 1.38 V and VDDL/2). LOP LO BUFFER LON TO MIXER LO PORT ~VDDL/2 84k fREF REF BUFFER PHASE/ FREQUENCY DETECTOR CHARGE PUMP LOR fLO LOA, LOB A, B COUNTERS FAST ACQUIRE fREF 8/9 LO BUFFER fLO FROM VCO 500 500 1.36V BIAS NOTE: ESD DIODE STRUCTURES OMITTED FOR CLARITY fREF STBY SWITCHES SHOWN WITH LO SYNTHESIZER ON Figure 4. LO Synthesizer The LO (and CLK) Synthesizer works in the following manner. The reference frequency, fREF, is buffered and divided by the value held in the R counter. The internal FREF is then compared to a divided version of the VCO frequency, fLO. The phase/ frequency detector provides UP and DOWN pulses whose width vary depending upon the difference in phase and frequency of its two input signals. The UP/DOWN pulses control the charge pump, making current available to charge the external low-pass loop filter when there is a discrepancy between the inputs of the PFD. The output of the low-pass filter feeds an external VCO whose output frequency, FLO, is driven such that its divided down version, FLO, matches that of FREF thus closing the feedback loop. The synthesized frequency is related to the reference frequency and the LO register contents as follows: fLO = (8 x LOB + LOA)/LOR x fREF Note, the minimum allowable value in the LOB register is 3 and its value must always be greater than that loaded into LOA. The stability, phase noise, spur performance, and transient response of the AD9870's LO (and CLK) synthesizers are determined by the external loop filter, the VCO, the N-divide factor, and the reference frequency, fREF. An excellent reference book on PLL synthesizers titled PLL Performance, Simulation and Design by Deen Banerjee is available for free at www.national.com. An example may help illustrate how the values of LOA, LOB, and LOR can be selected. Consider an application employing a 13 MHz crystal oscillator (i.e., fREF = 13 MHz) with the requirement that FREF = 100 kHz and fLO = 143 MHz (i.e., high-side injection with IF = 140.75 MHz and fSAMPLE = 18 MSPS). LOR is selected to be 130 such that fREF = 100 kHz. The N-divider factor is 1430, which can be realized by selecting LOB = 178 and LOA = 6. Figure 5. Equivalent Input of LO and REF Buffers Fast Acquire Mode The fast acquire circuit attempts to boost the output current when the phase difference between the divided-down LO (i.e., fLO) and the divided-down reference frequency (i.e., fREF) exceeds the threshold determined by the LOFA register. The LOFA register specifies a divisor for the fREF signal, and it is the period (T) of this divided-down clock that specifies the time interval which controls the fast acquire algorithm. Assume for the moment that the nominal charge pump current is at its lowest setting (i.e., LOI = 0) and denote this minimum current by I0. When the output pulse from the phase comparator exceeds T, the output current for the next pulse is 2I0; when the pulse is wider than 2T, the output current for the next pulse is 3I0, and so forth, up to eight times the minimum output current. If the nominal charge pump current is more than the minimum value (i.e., LOI > 0), the preceding rule is only applied if it results in an increase in the instantaneous charge pump current. If the charge pump current is set to its lowest value (LOI = 0) and the fast acquire circuit is enabled, the instantaneous charge pump current will never fall below 2I0, even when the pulsewidth is less than T. Thus the charge pump current when fast acquire is enabled is given by IPUMP-FA = IO x (1 + max (1, LOI, Pulsewidth/T)). -10- REV. 0 AD9870 The recommended setting for LOFA is LOR/16. Choosing a larger value for LOFA will increase T. Thus, for a given phase difference between the LO input and the fREF input, the instantaneous charge pump current will be less than that available for a LOFA value of LOR/16. Similarly, a smaller value for LOFA will decrease T, making more current available for the same phase difference. In other words, a smaller value of LOFA will enable the synthesizer to settle faster in response to a frequency hop than will a large LOFA value. Care must be taken to choose a value of LOFA which is large enough (values greater than four recommended) to prevent the loop from oscillating back and forth in response to a frequency hop. Table V. SPI Registers Associated with LO Synthesizer Address VDDC=3.0 V LOOP FILTER RD RBIAS LOSC 0.1 F CVAR COSC IOUTC CLKP CLKN AD9870 VCM = VDDC - RBIAS I BIAS > 1.6V fOSC > (2 LOSC (C VARACTOR//COSC))-1/2 CLK OSC. BIAS (Hex) 0x00 0x08 0x09 0x0A 0x0B 0x0C Bit Breakdown (7:0) (5:0) (7:0) (7:5) (4:0) (7:0) (6) (5) (4:2) (1:0) (3:0) (7:0) Width 8 6 8 3 5 8 1 1 3 2 4 8 Default Value 0xFF 0x00 0x38 0x5 0x00 0x1D 0 0 0 0 0x0 0x04 Name STBY LOR(13:8) LOR(7:0) LOA LOB(12:8 LOB(7:0) LOF LOINV LOI LOTM LOFA(13:8) LOFA(7:0) 2 IBIAS = 0.25, 0.35, 0.53, OR 0.85 mA Figure 6. External Loop Filter, Varactor and L-C Tank Are Required to Realize a Complete Clock Synthesizer 0x0D 0x0E CLOCK SYNTHESIZER The clock synthesizer is a fully programmable integer-N PLL capable of 2.2 kHz resolution at clock input frequencies up to 18 MHz and reference frequencies up to 25 MHz. It is similar to the LO synthesizer described previously in Figure 4 with the following exceptions: The AD9870 clock synthesizer circuitry includes a negativeresistance core so that only an external L-C tank circuit with a varactor is needed to realize a voltage controlled oscillator (VCO). Figure 6 shows the external components required to complete the clock synthesizer along with the equivalent input of the CLK input. The resonant frequency of the VCO is approximately determined by LOSC and the series equivalent capacitance of COSC and CVAR. As a result, LOSC, COSC, and CVAR should be selected to provide sufficient tuning range to ensure proper locking of the clock synthesizer The bias, IBIAS, of the negative-resistance core has four programmable settings. Lower equivalent Q of the L-C tank circuit may require a higher bias setting of the negativeresistance core to ensure proper oscillation. RBIAS should be selected such that the common-mode voltage at CLKP and CLKN is approximately 1.6 V. The synthesizer may be disabled via the CK standby bit to allow the user to employ an external synthesizer and/or VCO in place of those resident on the IC. Table VI. SPI Registers Associated with CLK Synthesizer Address * It does not include an 8/9 prescaler nor an A Counter. * It includes a negative-resistance core which when used in conjunction with an external varactor serves as the VCO. The 14-bit reference counter and 13-bit N-divider counter can be programmed via the following registers: CKR and CKN. The charge pump current is programmable via the CKI register from 0.625 mA to 5.0 mA using the following equation: IPUMP = (CKI + 1) x 0.625 mA. The fast acquire subcircuit of the charge pump is controlled by the CKFA register in the same manner as the LO synthesizer is controlled by the LOFA register. An on-chip lock detect function (enabled by the CKF bit) automatically increases the output current for faster settling during channel changes. The synthesizer may also be disabled using the CKOB standby bit located in the STBY register. (Hex) 0x00 0x01 0x10 0x11 0x12 0x13 0x14 Bit Breakdown Width (7:0) (3:2) (5:0) (7:0) (4:0) (7:0) (6) (5) (4:2) (1:0) (3:0) (7:0) 8 2 6 8 5 8 1 1 3 1 4 8 Default Value Name 0xFF 0 00 0x38 0x00 0x3C 0 0 0 0 0x0 0x04 STBY CKOB CKR(13:8) CKR(7:0) CKN(12:8) CKN(7:0) CKF CKINV CKI CKTM CKFA(13:8) CKFA(7:0) 0x15 0x16 REV. 0 -11- AD9870 IF1 LNA/MIXER The AD9870 contains a single-ended LNA followed by "Gilberttype" active mixer as shown in Figure 7a. The mixer's differential LO port is driven by an LO buffer stage which can be driven single-ended or differential. The LO signal level can range from 0.3 V p-p to 1.0 V p-p with negligible effect on performance. The input impedance at the IFIN pin is 360 2 pF ( 20%) and has no significant variation with respect to the programmable bias settings. Figure 7b. shows the S11 parameters of the AD9870 with the following LNA/Mixer bias setting: LNAB = 3, MIXB = 3. 180 LNA GAIN = 15 dB 180 MIXER GAIN = -5 dB Both the LNA and mixer have four programmable bias settings so that current consumption can be minimized for a given application. Figures 7c, 7d, and 7e show how the LNA and mixer's noise figure (NF), linearity (IIP3), conversion gain, current consumption and frequency response are all affected for a given LNA/Mixer bias setting. The measurements were taken at an IF = 73.35 MHz, an LO = 71.1 MHz, and supplies set to 3.0 V. Note, since the current consumption of the LNA/Mixer portion of the IC can be reduced by only 5 mA at most relative to the nominal current consumption of the entire IC in the high IIP3 mode (i.e., 42 mA), most applications will benefit with the AD9870's LNA/Mixer configured for the high bias mode (i.e., LNAB = 3, MIXB = 3 for SPI Port Register 1). 12 CONVERSION GAIN RBIAS LO INPUT = 0.3 TO 1.0 V p-p RGAIN MULTI-TANH V-I STAGE VCML 11 10 dB RF RIN = 360 9 NOISE FIGURE 8 DC SERVO LOOP 7 Figure 7a. Simplified Schematic of AD9870's LNA/Mixer J50 J100 6 0-0 0-1 0-2 0-3 1-0 1-1 1-2 1-3 2-0 2-1 2-2 2-3 3-0 3-1 3-2 3-3 LNA-MIXER POWER BIAS SETTING J25 Figure 7c. LNA/Mixer Noise Figure and Conversion Gain vs. Bias Setting 5 J200 9 LNA-MIXER CURRENT 8 7 J10 J400 0 IIP3 - dB 0 IIP3 -10 10 25 50 100 200 400 5 4 -J10 255-J163 AT 140 MHz -J400 166-J177 AT 240 MHz -J200 -15 3 2 -20 1 -J25 -J50 -J100 -25 0-0 0-1 0-2 0-3 1-0 1-1 1-2 1-3 2-0 2-1 2-2 2-3 3-0 3-1 3-2 3-3 LNA-MIXER POWER BIAS SETTING 0 Figure 7b. Input Impedance (i.e. S11) of the AD9870's IF1 Input Figure 7d. LNA/Mixer IIP3 and Current Consumption vs. Bias Setting -12- REV. 0 CURRENT - mA 323-J105 AT 73.35 MHz -5 6 AD9870 1 0 -1 -2 dB 3-3 BIAS SETTING 2-2 BIAS SETTING 1-1 BIAS SETTING -3 -4 -5 -6 10 The AAF tuning algorithm works in the following manner. The AD9870 measures the oscillation frequency of an on-chip RC oscillator relative to the frequency applied to the CLKP, CLKN pins. It then uses this measurement in conjunction with the AAR setting to program the capacitors of the AAF which sets the filters poles. The on-chip circuitry sets the capacitor-programming registers (CAPN and CAPP) to the required values based on the clock frequency and the AAR setting. The recommended -3 dB cutoff frequency is fCLK /3.2 (selected by setting AAR = 0x60) since it provides minimal signal attenuation in the passband region of fCLK /8 and sufficient attenuation of the potential alias components in the transition band region. For this setting the frequency-scaling resolution is sufficient to yield less than 10% tuning error with clock frequencies between 13 MHz and 18 MHz. Figure 9a shows the measured response of the antialias filter when it has been tuned with AAR = 0x60 at an ADC clock frequency of 18 MHz. The multiple curves show the possible tuning error due to the finite resolution of the tuning capacitors. In this example, the capacitor across the mixer load resistors yields a pole at 5 MHz, which degrades the mixer gain at 2.25 MHz by approximately 0.8 dB. The nominal -3 dB cutoff frequency of the antialias filter is 5.6 MHz. The nominal attenuation at the first alias (15.75 MHz) is 28 dB and falls at 60 dB/decade so that the nominal attenuation at 50 MHz is 60 dB. 5 0-1 BIAS SETTING 100 FREQUENCY - MHz 1000 Figure 7e. LNA/Mixer Frequency Response vs. Bias Setting Table VII. SPI Registers Associated with LNA/Mixer Address (Hex) 0x01 Bit Breakdown Width Default Value Name 0x01 0x03 (7:6) (5:4) (7) 2 2 1 0 0 0 LNAB MIXB ATTEN AAF FREQUENCY RESPONSE - dBFS ANTIALIAS FILTER -5 2.25MHz IF @ CLK = 18MSPS -15 -25 -35 The AD9870 includes a programmable continuous-time third order antialias filter (AAF) as shown in Figure 8. Its purpose is to suppress any noise or spectral components occurring at N x fCLK (fCLK/8) from aliasing back into the sigma-delta ADC's passband centered at fCLK/8. It consists of a programmable capacitor at the mixer output providing a real pole plus a second order programmable filter built into the VGA providing a complex pole pair. I-V 2ND ORDER LPF R2 -45 -55 -65 0.1 1 10 FREQUENCY - MHz 100 MIXER (5MHz LOWPASS) Gm0 R0 180 C0 Gm1 C1 C2 R1 Figure 9a. Antialias filter response with AAR = 0x60 and fCLK = 18 MHz. Note, the curves have been normalized individually to 0 dB at f0 = 2.25 MHz. C0 AND C1 CONSIST OF 36 NWELL CAPACITORS IN PARALLEL C3 CONSIST OF 36 POLY-POLY CAPACITORS IN PARALLEL Figure 8. Equivalent Circuit of Antialias Filter The AAF is typically tuned during the start-up phase of the AD9870. The user initiates tuning of the AAF by writing a value to the AAR (antialias response) register. The following two considerations should be noted when tuning the AAF response. First, the accuracy of the tuning algorithm is sensitive to on-chip digital noise. Thus, placing the ADC in standby (i.e., register STBY) prior to tuning the AAF is recommended. Second, although the default setting of the AAR register is 0x00, writing 0x00 is not recommended since all subsequent writes to this register will be ignored until power to the AD9870 is reapplied to reset this register. Since the frequency measurements are performed relative to the clock frequency, the AAF's normalized frequency response remains relatively independent of the ADC clock frequency. There is guaranteed to be sufficient range in the programmable capacitor arrays to support the response of Figure 9a for clock frequencies between 13 MHz and 18 MHz with the resolution indicated. Also, the normalized frequency response of the AAF remains relatively independent of the programmed -3 dB cutoff frequency over a 13 MHz to 18 MHz frequency range as shown in Figure 9b. If the user specifies an unattainable response, the on-chip circuitry sets CAPN and/or CAPP to the limit of their ranges and also sets the ERRN and/or ERRP bit to indicate that the specified response cannot be supported. REV. 0 -13- 5 Table VIII. SPI Registers Associated with AAF fCLK/8 AAF FREQUENCY RESPONSE - dBFS -5 -15 -25 -35 -45 -55 -65 Address (Hex) fCLK = 13MSPS Bit Breakdown Width (7:0) 5 (4:0) 5 (4:0) 8 1 5 1 15 Default Value 0x00 0 0x0 0 0x0 Name AAR ERRN CAPN ERRP CAPP 0x1C 0x1D 0x1E fCLK = 15MSPS fCLK = 18MSPS -75 -85 -95 0.01 VARIABLE GAIN AMPLIFIER OPERATION WITH AUTOMATIC GAIN CONTROL 0.1 1 FREQUENCY - MHz 10 Figure 9b. Measured Normalized AAF Frequency Response for AAR = 0 x 60 Setting with fCLK = 13, 15, and 18 MHz 5 AAF FREQUENCY RESPONSE - dBFS AAR = 0 -5 -15 AAR = 0 -25 -35 AAR = 0 60 C0 30 The AD9870 contains a variable gain amplifier (VGA) as well as all of the necessary signal estimation and control circuitry to implement automatic gain control (AGC) as shown in Figure 10. The AGC control circuitry provides a high degree of programmability to allow the user to optimize the AGC response as well as the AD9870's dynamic range for a given application. The VGA is programmable over a 25 dB (typ) range and implemented in the same circuitry as the AAF circuitry previously discussed. Since its input is self-biasing and presents a high impedance to the mixer output load, the differential output signal appearing at the mixer output (MXOP, MXON) must be ac coupled to the VGA input (IF2P, IF2N) with 0.1 F ceramic chip capacitors. Note, an external 20 k resistor in parallel with a 0.1 F capacitor from VCM (Pin 13) to GNDA is required to ensure common-mode compatibility between the ADC input and VGA output. The purpose of the VGA is to extend the usable dynamic range of the AD9870 by allowing the sigma-delta ADC to digitize low level signals in the presence of larger unfiltered interferer signals without saturation or "clipping" the ADC. The VGA can operate in either a user controlled variable gain control mode or automatic gain control (AGC) mode. The VGA may also be disabled using the VGA standby bit located in the STBY register. Note, ideally the quiescent current of the VGA circuitry should reduced from 6 mA to 0 mA when the standby is invoked. However, it has been found that the standby current increases to 1.3 mA a few seconds (temperature dependent) after placing the VGA in standby. Hence, the user is recommended to write to the STBY register periodically (0.1 kSPS) and toggle the VGA bit (i.e., write 0 followed by 1) to ensure that the standby current remains at approximately 0 mA. fCLK 20 IF2P IF2N I Q -45 -55 -65 0.1 1 10 FREQUENCY - MHz 100 Figure 9c. Measured AAF Frequency Response for Different AAR Settings with fCLK = 18 MHz Changing the AAR setting from the recommended value of 0 x 60 scales the frequency axis in an inverse way as shown in Figure 9c. For example, to scale the frequency response down by a factor of 1.5 set the AAR register to 1.5 times 0 x 60 (i.e., 0 x 90). This AAR setting will not cause an error flag to be set for fCLK = 18 MHz since the 3.7 MHz cutoff is within the guaranteed range. For fCLK = 18 MHz, this AAR setting would increase the attenuation at the first alias by 10 dB, lower the -3 dB cutoff from 5.6 MHz to 3.7 MHz, and reduce the mixer gain by 0.8 dB due to the reduced mixer pole frequency. However, reducing fCLK to 13 MHz while using the same AAR setting in many parts may cause a deviation in the normalized frequency response since the -3 dB cutoff of 2.7 MHz is well below the 3.5 MHz lower limit. In general, -3 dB cutoff frequencies can be approximated by the following equation: f-3 dB = (fCLK/3.2) x (0 x 60/AAR) where AAR is the hexadecimal contents of the AAR register and 0 x 60 is its hexadecimal default setting. VGA/ AAF - ADC ej(2 fCLK/8)t DEC1 20 ADC CLIP POINT ABS(I[N])+ABS(Q[N]) OLW VGA DAC 1 (1-Z -1) AGC CONTROL AGCR REF LEVEL GCN GCP CDAC fCLK/20 Figure 10. Functional Block Diagram of VGA and AGC -14- REV. 0 ) AD9870 Variable Gain Control When in variable gain mode, the gain of the VGA can be adjusted by writing to the 16-bit AGCR register. Note, proper loading of the AGCR register requires that address 0x03 always be written prior to 0x04. The maximum update rate of the AGCG register is fCLK/100. The MSB of this register is the bit which enables 16 dB of attenuation in the preamp. This feature allows the AD9870 to cope with large level signals beyond the VGA's range to prevent overloading of the ADC. The gain of the VGA is set by an 8-bit control DAC which provides a differential control signal to the VGA appearing at pins GCP and GCN. Two external 0.1 F capacitors, CDAC, from GCP and GCN to analog ground, are required to "smooth" or filter the DAC's output each time it updates. Note, the differential equivalent value of these two capacitors (i.e., CDAC/2) in combination with the DAC's programmable output resistance sets the -3 dB bandwidth and time constant associated with this RC network. Automatic Gain Control (AGC) A description of the AGC control algorithm and the user adjustable parameters follows. First consider the situation in which the in-band signal is bigger than all out-of-band signals. In this case, the amplitude of the in-band signal will be tracked to the programmed reference level by the AGC using the output of the digital estimation block. If the difference is negative (i.e., the signal is too large), the gain is decreased with a proportionality constant determined by the AGCA setting. Large AGCA values result in large gain changes thus rapid tracking of changes in signal strength. If the difference between the target and estimated signal level is positive (i.e., the signal is too small), the gain is increased but now the proportionality constant is determined by both the AGCA and AGCD settings. AGCD is effectively subtracted from AGCA, so large AGCD results in smaller gain changes and thus slower tracking of fading signals. The 4-bit code in the AGCA field sets the raw bandwidth of the AGC loop. With AGCA = 0, the AGC loop bandwidth is at its minimum of 50 Hz. Each increment of AGCA increases the loop bandwidth by a factor of 21/2; thus the maximum bandwidth is 9 kHz. A general expression for the attack bandwidth is BWA = 50 x (fCLK/18 MHz) x 2(AGCA/2) Hz (2) The attack time may be estimated from the loop bandwidth if one assumes that the loop dynamics are essentially that of a single-pole system as described by the following equation. tATTACK = 2.2/(100 x x 2AGCA/2) = 0.35/BWA (3) This approximation is good if the extra pole caused by the RC filter on the DAC output is at a sufficiently high frequency. If the RC pole is placed at four times the raw AGC pole (i.e., RC = 1/(8 x x BW)) then Equation 3 yields an attack time which is high by about 25%. A more accurate formula for this case is to replace the 2.2 in the numerator of Equation 3 by 1.7. The 4-bit code in the AGCD field sets the ratio of the attack time to the decay time in the amplitude estimation circuitry. When AGCD is zero, this ratio is one. Incrementing AGCD multiplies the decay time-constant by 21/2, allowing a 180:1 range in the decay time relative to the attack time. The decay time may be computed from tDECAY = tATTACK x 2 (AGCD/2) (4) The 4-bit code in the AGCO field sets the weighting applied to gain updates when overload is detected. Each increment in AGCO doubles the weighting factor. At the highest AGCO setting, each reset event will cause a 6 dB reduction in the VGA gain. Lastly, the AGCF bit reduces the DAC source resistance by a factor of 8. This facilitates fast acquisition by lowering the RC time constant which is formed with the external capacitors connected from the GCP and GCN pins to ground. For an overshoot-free step response in the AGC loop, the capacitors should be chosen such that the RC time constant is less than one quarter that of the raw loop. Specifically, RC 1/(8 BW) (5) where R is the resistance between the GCN and GCP pins and ground (30 k 30% if AGCF = 0, <3.8 k if AGCF = 1) and BW is the raw loop bandwidth. Note that with C chosen at this upper limit, the loop bandwidth increases by approximately 30%. The gain of the VGA is automatically adjusted when the AGC is enabled via the AGCR register. In this mode, the gain of the VGA is continuously updated in an attempt to ensure that the maximum signal level into the ADC does not exceed a fixed analog ADC clip level and that the rms output level of the ADC is equal to a programmable reference level. This programmable level can be set at 3 dB, 6 dB, 9 dB, 12 dB, and 15 dB below the ADC saturation (clip level) by writing values from 1 to 5 to the 3-bit AGCR field. Note, the ADC clip level is defined to be -2 dBFS of its full-scale (i.e., 0.28 V rms). If AGCR is 0, automatic gain control is disabled. The AGC control loop and estimation circuitry are implemented both in the analog and digital domain to cope with out-of-band interferers and in-band signals which could otherwise overload the ADC. If the largest signal into the ADC falls outside the passband of the first stage digital filter and exceeds the ADC clip level of -2 dBFS, a control loop based on an analog comparator is used to reduce the VGA gain and prevent ADC clipping. If the largest signal into the ADC is the target signal (and/or interferer) falling within the passband defined by the first decimation filter (but below the ADC clip level), a control loop based on a digital estimation of the signal power is used to control the VGA gain. Referring to Figure 10, an analog comparator is used to compare the VGA output (or ADC input) to a reference threshold which is close to that of the ADC clip level. The output of the comparator will be a digital signal named "OLW" which drives the digital integrator within the AGC control loop when an overload condition is detected. Note, the detection of an overload condition via this analog signal estimation path takes precedence over the digital signal estimation path in the AGC control loop until the analog overload condition is removed. For signals falling within the passband of the first stage decimate-by-20 digital filter, the rms power of the I and Q signal is estimated digitally by the following equation: XEST[N] = ABS(I[N]) + ABS(Q[N]) (1) As a result, the VGA and other registers involved in the AGC algorithm are updated at fCLK/20. The number of overload and ADC reset occurrences within the final I/Q update rate of the AD9870 as well as the AGC value (8 MSBs) can be read from the SSI data upon proper configuration. REV. 0 -15- AD9870 Table IX. SPI Registers Associated with AGC Address DECIMATION FILTER (Hex) 0x03 0x04 0x05 0x06 Bit Breakdown (7) (6:0) (7:0) (7:4) (3:0) (7:4) (3:0) (2:0) Width 1 7 8 4 4 4 4 3 Default Value 0 0x3F 0xFF 0 0 0 0 0 Name ATTEN AGCG(14:8) AGCG(7:0) AGCA AGCD AGCO AGCD AGCR The decimation filter consists of a complex mix by fCLK/8 and a cascade of three linear phase FIR filters: DEC1, DEC2, and DEC3 as shown in Figure 12. DEC1 downsamples by a factor of 20 using a fourth-order comb filter. DEC2 also uses a fourthorder comb filter, but its decimation factor is set by the M control register. DEC3 is a decimate-by-3 FIR filter. COS DEC1 DATA FROM MODULATOR SIN SINC4 FILTER 20 M I DEC2 SINC4 FILTER M+1 DEC3 FIR FILTER 3 COMPLEX DATA TO Q SSI PORT System Noise Figure (NF) vs. VGA (or AGC) Control The AD9870's system NF is a strong function of the gain setting of the VGA. The noise present at the output of the VGA and input of the ADC is relatively large and independent of the VGA setting. Under small signal conditions in which the VGA is set to its maximum gain, this noise referred back to the input of the LNA's input has less of an effect on raising the AD9870's system NF. However, under large signal conditions in which the gain of the VGA must be reduced to prevent ADC clipping, this noise quickly becomes a significant contributor in determining the AD9870's overall NF. Figure 11 shows how the NF of the AD9870 in AGC mode remains relatively constant as an interferer signal input power is increased until its power reaches a programmed reference level (i.e., -3 dB) at which point the NF degrades almost 1 dB per dB as the interferer signal is increased beyond this point, forcing the VGA gain to decrease. As a result, it is recommended that the AGC referenced level be set to 3 (i.e., AGCR = 1) to maintain the best possible NF over the widest input signal range. 45 42 39 36 NOISE FIGURE - dB Figure 12. Decimation Filter Architecture Figure 13a shows the response of the complete decimation filter on a linear frequency axis for frequencies up to the third alias. As this figure shows, the alias with the least attenuation is located at the lower end of the third alias band and has an attenuation of 83 dB. 0 -20 FOLDING POINT 5kHz PASSBAND 88dB ATTENUATION (MIN) 83dB ATTENUATION (MIN) -40 dB >100dB ATTENUATION -60 -80 150 -100 ADC CLIPS AT -24 dBm MEAN AGC VALUE 0 10 20 100 30 40 FREQUENCY - kHz 50 60 70 33 30 27 24 21 18 15 12 NOISE FIGURE 50 MEAN AGC VALUE Figure 13a. Frequency Response for fCLKOUT = 20 kHz, Showing the First Three Alias Bands 0 -50 -100 9 -150 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 INTERFERER AMPLITUDE - dBm Figure 13b shows the full response of the decimation filter with the decimation factor set to 60 on a logarithmic frequency scale, while Figure 13c shows the folded frequency response on a linear frequency scale and Figure 13d shows a blowup of the passband. The location of the cutoff frequency shown in Figure 13b is inversely proportional to the decimation factor. However, since both DEC1 and DEC2 are fourth-order comb filters, their combination is also a fourth-order comb filter and thus the shapes of the frequency responses shown in Figures 13c and 13d are independent of the decimation factor. Figure 11. Noise Figure vs. Interferer Signal Level with an IF = 73.35 MHz and CLK = 18 MSPS and AGCR = 1 -16- REV. 0 AD9870 0 Evaluation Board and Software -20 -40 -60 -80 -100 10-4 10-3 10-2 10-1 BASEBAND FREQUENCY - Relative to fCLK The evaluation board along with its accompanying software provide a simple means to evaluate the AD9870. The block diagram in Figure 14 shows the major blocks of the evaluation board. The evaluation board is designed to be flexible allowing the user to configure it for different potential applications. The power supply distribution block provides filtered, adjustable voltages to the various supply pins of the AD9870. In the IF Input signal path, component pads are available to implement different IF impedance matching networks. The LO and CLK signals can be externally applied or internally derived from a user-supplied VCO Module interface daughter board. The reference for the on-chip LO and CLK synthesizers can be applied via the external FREF input or an on-board crystal oscillator. dB Figure 13b. Decimator Frequency Response 0 IF LO INPUT INPUT VCO MODULE INTERFACE AD9870 OR AD9874 FREF INPUT -20 MIXER OUTPUT CRYSTAL OSCILLATOR -40 -60 XILINX SPARTON FPGA AD9870/AD9874 POWER SUPPLY DISTRIBUTION IDT FIFO (OPTIONAL) NIDAQ 68-PIN CONNECTOR dB -80 CLK INPUT EPROM -100 0 0.25 NORMALIZED FREQUENCY - Relative to fOUT 0.50 Figure 14. Evaluation Board Platform Figure 13c. Folded Decimator Frequency Response As Figure 13d shows, the gain variation across the passband is approximately 0.4 dB. Normalization of full-scale is accurate to within 0.4 dB across all decimation modes. 0 The evaluation board is designed to interface to a PC via a National Instruments PCI-DIO-32HS digital IO card. A XILINX FPGA formats the data between the AD987x and digital I/O board. Software developed using National Instruments LabVIEWTM and provided as MS WindowsTM executable programs is supplied for the configuration of the SPI port registers and evaluation of the AD9870 output data. These programs have a convenient graphical user interface allowing for easy access to the various SPI port configuration registers and real time frequency analysis of output data. -20 -40 dB -60 -80 -100 0 NORMALIZED FREQUENCY - Relative to fOUT 0.25 Figure 13d. Passband Frequency Response of the Decimator REV. 0 -17- AD9870 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 1 0.354 (9.00) BSC SQ 48 37 36 TOP VIEW (PINS DOWN) 0.276 (7.00) BSC SQ 25 COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09) 0 MIN 12 13 24 0.019 (0.5) 0.011 (0.27) BSC 0.006 (0.17) 7 0 0.006 (0.15) SEATING 0.002 (0.05) PLANE 0.057 (1.45) 0.053 (1.35) -18- REV. 0 -19- -20- C01626-4.5-4/01(0) PRINTED IN U.S.A. This datasheet has been download from: www..com Datasheets for electronics components. |
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